用VHDL描述下列器件的功能: (1)4选1数据选择器; (2)2线-4线译码器; (3)时
问题详情
用VHDL描述下列器件的功能: (1)4选1数据选择器; (2)2线-4线译码器; (3)时钟R-S触发器; (4)带复位端Clear和置位端Preset、延迟Tpd为20ns的响应CP下降沿的J-K触发器; (5)主从J-K触发器; (6)集成计数器74163; (7)集成移位寄存器74194。
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参考答案
正确答案:(1)4选1数据选择器。ENTITY mux41 ISPORT(ena0a1d0d1d2d3:IN Bit;F:OUT Bit);END mux41;ARCHITECTURE bch_mux41 OF mux41 ISBEGINPROCESS(ena1a0d3d2d1d0)BEGINIF(en=‘1’)THENIF(al=‘0’AND a0=‘0’)THENf<=d0;ELSIF(al=‘0’AND a0=‘1’)THENf<=d1;ELSIF(a1=‘1’AND a0=‘0’)THENf<=d2:ELSEf<=d3;ENDIF;ELSEf<=‘0’;ENDIF;END PROCESS;END bch_mux41;(2)2线一4线译码器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY b0-2-4 ISPORT(ena0a1:IN STD_LOGIC;YOY1Y2Y3:OUT STD_LOGICO);END b0-2-4;ARCHITECTURE rtl OF b0-2-4 ISSIGNAL tmp_IN:STD_LOGIC_VECTOR(IDOWNTO 0);SIGNAL tmp_OUT:STD_LOGIC_VECTOR(3DOWNTO 0);BEGINtmp_IN<=al&a0;PROCESS(tmp_INen)BEGINIF(en=‘0’)THENCASS tmp_IN ISWHEN“00”=>tmp_OUT<=“1110”;WHEN“01”=>tmp_OUT<=“1101”;WHEN“10”=>tmp_OUT<=“1011”;WHEN“11”=>tmp_OUT<=“0111”;WHEN OUTTHERS=>tmp_OUT<=“1111”;END CASS;ELSEtmp_OUT<=“1111”;END IF;Y0<=tmp_OUT(0);Yl<=tmp_OUT(1);Y2<=tmp_OUT(2);Y4<=tmp_OUT(3);END PROCESS:END rt1;(3)时钟R-S触发器。ENTITY R-S-FFPORT(rsCLK:IN Bit;qnq:BUFFER Bit);END R-S-FF:ARCH工TECTURE rsff OF R-S-FFISBEGINASSERT NOT(r=‘1’AND s=‘1’REPORT“Control∣error“SEVERITV Error;PROCESS(rsCLK)BEGINIF CLK=‘1’THENq<=S OR(NOT r AND q);nq<=NOT(S OR(NOT r AND q));END IF;END PROCESS;END rsff;(4)带复位端Clear和置位端Preset、输出延迟Tpd为20ns响应CP下降沿的J-K触发器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JKff ISPORT(clearpresetCLKJK:INSTD LOGIC:qNq:OUT STD_LOGIC);END JKff;ARCHITECTURE rl OF JKff ISPROCESS(clearpresetCLKJK)BEGINIF(clear=‘0’)THENq<=‘0’;Nq<=‘1’;ELSIF(preset=‘0’)THENq<=‘1’;Nq<=‘0’:ELSIF(CLK’EVENT AND CLK=‘0’)THENIF(J=‘0’)AND(K=‘1’)THENq<=‘0’ AFTER 20ns;Nq<=‘1’AFTER 20ns:ELSIF(J=‘1’)AND(K=‘0’)T既Nq<=‘1 ’AFTER 20ns;Nq<=‘0’AFTER 20ns:ELSIF(J=‘1’)AND(K=‘1’)THENq<=NOT q AFTER 20ns;Nq<=NOT Nq AFTER 20ns:ENDIF;END PROCESS;END rtl;(5)主从J-K触发器。可根据主从J-K触发器特点自行编程。(6)集成计数器74163。ENTITY counterl6 ISPORT(cridcp.cttctp:IN Bit;d:IN Bit VECTOR(3DOWNTO 0);q:BUFFER Bit_Vector(3DOWNTO 0);co:OUT Bit);END counter16;ARCHITECTURE behave_ctr16 OF counterl 6 ISBEGINPROCESS(cp)BEGINIF(cp=‘1’)THENIF cr=‘0’THENq<=“0000”;ELSIF id=‘0’THENq<=d;ELSIF(ctt=‘1’AND ctp=‘1’)THENIF q=“1111”THENq<=“0000”;ELSEq<=q+1;END IF;END IF;END IF;END PROCESS;c0<=‘1’WHEN(q=“1111”AND ctt=‘l’)ELSE‘0’;END bch_ctr16;(7)集成移位寄存器74194。(请读者自行编写)。
4选1数据选择器。ENTITYmux41ISPORT(en,a0,a1,d0,d1,d2,d3:INBit;F:OUTBit);ENDmux41;ARCHITECTUREbch_mux41OFmux41ISBEGINPROCESS(en,a1,a0,d3,d2,d1,d0)BEGINIF(en=‘1’)THENIF(al=‘0’ANDa0=‘0’)THENf<=d0;ELSIF(al=‘0’ANDa0=‘1’)THENf<=d1;ELSIF(a1=‘1’ANDa0=‘0’)THENf<=d2:ELSEf<=d3;ENDIF;ELSEf<=‘0’;ENDIF;ENDPROCESS;ENDbch_mux41;(2)2线一4线译码器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYb0-2-4ISPORT(en,a0,a1:INSTD_LOGIC;YO,Y1,Y2,Y3:OUTSTD_LOGICO);ENDb0-2-4;ARCHITECTURErtlOFb0-2-4ISSIGNALtmp_IN:STD_LOGIC_VECTOR(IDOWNTO0);SIGNALtmp_OUT:STD_LOGIC_VECTOR(3DOWNTO0);BEGINtmp_IN<=al&a0;PROCESS(tmp_IN,en)BEGINIF(en=‘0’)THENCASStmp_INISWHEN“00”=>tmp_OUT<=“1110”;WHEN“01”=>tmp_OUT<=“1101”;WHEN“10”=>tmp_OUT<=“1011”;WHEN“11”=>tmp_OUT<=“0111”;WHENOUTTHERS=>tmp_OUT<=“1111”;ENDCASS;ELSEtmp_OUT<=“1111”;ENDIF;Y0<=tmp_OUT(0);Yl<=tmp_OUT(1);Y2<=tmp_OUT(2);Y4<=tmp_OUT(3);ENDPROCESS:ENDrt1;(3)时钟R-S触发器。ENTITYR-S-FFPORT(r,s,CLK:INBit;q,nq:BUFFERBit);ENDR-S-FF:ARCH工TECTURErsffOFR-S-FFISBEGINASSERTNOT(r=‘1’ANDs=‘1’REPORT“Control∣error“SEVERITVError;PROCESS(r,s,CLK)BEGINIFCLK=‘1’THENq<=SOR(NOTrANDq);nq<=NOT(SOR(NOTrANDq));ENDIF;ENDPROCESS;ENDrsff;(4)带复位端Clear和置位端Preset、输出延迟Tpd为20ns,响应CP下降沿的J-K触发器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJKffISPORT(clear,preset,CLK,J,K:INSTDLOGIC:q,Nq:OUTSTD_LOGIC);ENDJKff;ARCHITECTURErlOFJKffISPROCESS(clear,preset,CLK,J,K)BEGINIF(clear=‘0’)THENq<=‘0’;Nq<=‘1’;ELSIF(preset=‘0’)THENq<=‘1’;Nq<=‘0’:ELSIF(CLK’EVENTANDCLK=‘0’)THENIF(J=‘0’)AND(K=‘1’)THENq<=‘0’AFTER20ns;Nq<=‘1’AFTER20ns:ELSIF(J=‘1’)AND(K=‘0’)T既Nq<=‘1’AFTER20ns;Nq<=‘0’AFTER20ns:ELSIF(J=‘1’)AND(K=‘1’)THENq<=NOTqAFTER20ns;Nq<=NOTNqAFTER20ns:ENDIF;ENDPROCESS;ENDrtl;(5)主从J-K触发器。可根据主从J-K触发器特点自行编程。(6)集成计数器74163。ENTITYcounterl6ISPORT(cr,id,cp.ctt,ctp:INBit;d:INBitVECTOR(3DOWNTO0);q:BUFFERBit_Vector(3DOWNTO0);co:OUTBit);ENDcounter16;ARCHITECTUREbehave_ctr16OFcounterl6ISBEGINPROCESS(cp)BEGINIF(cp=‘1’)THENIFcr=‘0’THENq<=“0000”;ELSIFid=‘0’THENq<=d;ELSIF(ctt=‘1’ANDctp=‘1’)THENIFq=“1111”THENq<=“0000”;ELSEq<=q+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;c0<=‘1’WHEN(q=“1111”ANDctt=‘l’)ELSE‘0’;ENDbch_ctr16;(7)集成移位寄存器74194。(请读者自行编写)。